1. Field of the Invention
The present invention relates to a wafer scale integration semiconductor device comprising a plurality of semiconductor circuit modules all integrated on an entire wafer or a fraction of a wafer and more particularly, to the architectures and methods to enable the economical implementation of a wafer-scale integrated circuit with high performance.
More specifically, this invention relates to a wafer-scale-integration system including (1) a novel configurable-interconnect architecture, (2) a novel high-speed parallel on-wafer bus system, (3) a unique layout that allows testing and configuration using simple probes, (4) a special coding method for establishing unique addresses for each circuit module, (5) a novel power supply switch, and (6) unique algorithms for configuring full-wafer or partial-wafer circuits.